The present invention relates generally to improved polishing pads used to polish and/or planarize substrates, particularly metal or metal-containing substrates during the manufacture of a semiconductor device. Specifically, this invention relates to pads having an optimized combination of physical properties for improved pad performance.
Chemical-mechanical planarization (xe2x80x9cCMPxe2x80x9d) is a process currently practiced in the semiconductor industry for the production of flat surfaces on integrated circuits devices. This process is discussed in xe2x80x9cChemical Mechanical Planarization of Microelectronic Materialsxe2x80x9d, J. M. Steigerwald, S. P. Murarka, R. J. Gutman, Wiley, 1997, which is hereby incorporated by reference in its entirety for all useful purposes. Broadly speaking, CMP involves flowing or otherwise placing a polishing slurry or fluid between an integrated circuit device precursor and a polishing pad, and moving the pad and device relative to one another while biasing the device and pad together. Such polishing is often used to planarize: i. insulating layers, such as silicon oxide; and/or ii. metal layers, such as tungsten, aluminum, or copper.
As semiconductor devices become increasingly complex (requiring finer feature geometries and greater numbers of metallization layers), CMP must generally meet more demanding performance standards. A relatively recent CMP process has been the fabrication of metal interconnects by the metal damascene process (see for example, S. P. Murarka, J. Steigerwald, and R. J. Gutmann, xe2x80x9cInlaid Copper Multilevel Interconnections Using Planarization by Chemical Mechanical Polishingxe2x80x9d, MRS Bulletin, pp. 46-51, June 1993, which is hereby incorporated by reference in its entirety for all useful purposes).
With damascene-type polishing, the polished substrate is generally a composite rather than a homogenous layer and generally comprises the following basic steps: i. a series of metal conductor areas (plugs and lines) are photolithographically defined on an insulator surface; ii. the exposed insulator surface is then etched away to a desired depth; iii. after removal of the photoresist, adhesion layers and diffusion barrier layers are applied; iv. thereafter, a thick layer of conductive metal is deposited, extending above the surface of the insulator material of the plugs and lines; and v. the metal surface is then polished down to the underlying insulator surface to thereby produce discrete conductive plugs and lines separated by insulator material.
In the ideal case after polishing, the conductive plugs and lines are perfectly planar and are of equal cross-sectional thickness in all cases. In practice, significant differences in thickness across the width of the metal structure can occur, with the center of the feature often having less thickness than the edges. This effect, commonly referred to as xe2x80x9cdishingxe2x80x9d, is generally undesirable as the variation in cross-sectional area of the conductive structures can lead to variations in electrical resistance. Dishing arises because the harder insulating layer (surrounding the softer metal conductor features) polishes at a slower rate than the metal features. Therefore, as the insulating region is polished flat, the polishing pad tends to erode away conductor material, predominantly from the center of the metal feature, which in turn can harm the performance of the final semiconductor device.
The present invention is directed to polishing pads for CMP having low elastic recovery during polishing, while also exhibiting significant anelastic properties relative to many known polishing pads. In some embodiments, the pads of the present invention further define: i. a surface roughness of about 1 to about 9 microns Ra; ii. a hardness of about 40 to about 70 Shore D; and iii. a tensile Modulus up to about 2000 MPa at 40xc2x0 C. In one embodiment, the polishing pads of the present invention define a ratio of Exe2x80x2 at 30xc2x0 and 90xc2x0 C. being less than about 5, preferably less than about 4.6 and more preferably less than about 3.5. In other embodiments of the present invention, the polishing pad defines a ratio of Exe2x80x2 at 30xc2x0 C. and 90xc2x0 C. from about 1.0 to about 5.0 and a KEL from about 100 to about 1000 (1/Pa) (40xc2x0 C.). In other embodiments, the polishing pad has a surface roughness of about 2 to about 7 micron Ra, a hardness of about 45 to about 65 Shore D, a Modulus Exe2x80x2 of about 150 to about 1500 MPa at 40xc2x0 C., a KEL of about 125 to about 850 (1/Pa at 40xc2x0 C.) and a ratio of Exe2x80x2 at 30xc2x0 C. and 90xc2x0 C. of about 1.0 to about 4.0. In yet other embodiments, the polishing pads of the present invention have a surface roughness of about 3 to about 5 micron Ra, a hardness of about 55 to about 63 Shore D, a Modulus Exe2x80x2 of 200 to 800 MPa at 40xc2x0 C., KEL of 150 to 400 (1/Pa at 40xc2x0 C.) and a ratio of Exe2x80x2 at 30xc2x0 C. and 90xc2x0 C. of 1.0 to 3.5.
In one embodiment, the modulus value can be as low as about 100 MPa, provided the pad is (sufficiently) hydrolytically stable. Such stability is characterized by substantially stable pad performance as the pad is increasingly subjected to water based fluids.
In other embodiments, the present invention is directed to a process for polishing metal damascene structures on a semiconductor wafer by: i. pressing the wafer against the surface of a pad in combination with an aqueous-based liquid that optionally contains sub-micron particles; and ii. providing mechanical or similar-type movement for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer.
The preferred pads of the present invention are characterized by high-energy dissipation, particularly during compression, coupled with high pad stiffness. Preferably, the pad exhibits a stable morphology that can be reproduced easily and consistently. Furthermore, the pad surface preferably resists glazing, thereby requiring less frequent and less aggressive conditioning and resulting in low pad wear and longer pad life. In one embodiment, the polishing pads of the present invention exhibit low dishing of metal features, low oxide erosion, reduced pad conditioning, high metal removal rates, good planarization, and/or lower defectivity (scratches and light point defects), relative to known polishing pads.
The pads of the present invention can be made in any one of a number of different ways. Indeed, the exact composition generally is not important so long as the pads exhibit low elastic recovery during polishing. Although urethanes are a preferred pad material, the present invention is not limited to polyurethanes and can comprise virtually any chemistry capable of providing the low elastic recovery described herein. The pads can be, but are not limited to, thermoplastics or thermosets and can be filled or unfilled. The pads of the present invention can be made by any one of a number of polymer processing methods, such as but not limited to, casting, molding, coating, extruding, photoimaging, printing, sintering, and the like.
In a preferred embodiment, the pads of the present invention have one or more of the following attributes:
1. Dishing of conductive features such as conductors and plugs is minimal,
2. Die-level planarity is achieved across the wafer surface, and/or
3. Defects such as scratches and light-point-defects are minimal and do not adversely effect electrical performance of the semiconductor device.
The above attributes can be influenced and sometimes controlled through the physical properties of the polishing pad, although pad performance is also dependent on all aspects of the polishing process and the interactions between pad, slurry, polishing tool, and polishing conditions, etc.
In one embodiment, the pads of the present invention define a polishing surface which is smooth, while still maintaining micro-channels for slurry flow and nano-asperities to promote polishing. One way to minimize pad roughness is to construct an unfilled pad, since filler particles tend to increase pad roughness.
Pad conditioning can also be important. Sufficient conditioning is generally required to create micro-channels in the pad surface and to increase the hydrophilicity of the pad surface, but over-conditioning can roughen the surface excessively, which in turn can lead to an increase in unwanted dishing.
The pads of the present invention preferably have low elastic rebound. Such rebound can often be quantified by any one of several metrics. Perhaps the simplest such metric involves the application of a static compressive load and the measurement of the percent compressibility and the percent elastic recovery. Percent compressibility is defined as the compressive deformation of the material under a given load, expressed as a percentage of the pad""s original thickness. Percent elastic recovery is defined as the fraction of the compressive deformation that recovers when the load is removed from the pad surface.
However, the above test for elastic rebound may be flawed, since polishing is a dynamic process and may not be adequately defined using static parameters. Also, polishing pads tend to be polymeric exhibiting viscoelastic behavior; therefore, perhaps a better method of characterization is to use the techniques of dynamic mechanical analysis (see J. D. Ferry, xe2x80x9cViscoelastic Properties of Polymersxe2x80x9d, New York, Wiley, 1961 which is hereby incorporated by reference in its entirety for all useful purposes).
Viscoelastic materials exhibit both viscous and elastic behavior in response to an applied deformation. The resulting stress signal can be separated into two components: an elastic stress which is in phase with the strain, and a viscous stress which is in phase with the strain rate but 90 degrees out of phase with the strain. The elastic stress is a measure of the degree to which a material behaves as an elastic solid; the viscous stress measures the degree to which the material behaves as an ideal fluid. The elastic and viscous stresses are related to material properties through the ratio of stress to strain (this ratio can be defined as the modulus). Thus, the ratio of elastic stress to strain is the storage (or elastic) modulus and the ratio of the viscous stress to strain is the loss (or viscous) modulus. When testing is done in tension or compression, Exe2x80x2 and Exe2x80x3 designate the storage and loss modulus, respectively.
The ratio of the loss modulus to the storage modulus is the tangent of the phase angle shift (xcex4) between the stress and the strain. Thus,
Exe2x80x3/Exe2x80x2=Tan xcex4
and is a measure of the damping ability of the material.
Polishing is a dynamic process involving cyclic motion of both the polishing pad and the wafer. Energy is generally transmitted to the pad during the polishing cycle. A portion of this energy is dissipated inside the pad as heat, and the remaining portion of this energy is stored in the pad and subsequently released as elastic energy during the polishing cycle. The latter is believed to contribute to the phenomenon of dishing.
It has been discovered that pads which have relatively low rebound and which absorb the relatively high amounts of energy during cyclic deformation tend to cause relatively low amounts of dishing during polishing. There are several parameters which may be used to describe this effect quantitatively. The simplest is Tan xcex4, defined above. However, perhaps a better parameter for predicting polishing performance is known as the xe2x80x9cEnergy Loss Factorxe2x80x9d. ASTM D4092-90 (xe2x80x9cStandard Terminology Relating to Dynamic Mechanical Measurements of Plasticsxe2x80x9d which is incorporated by reference in its entirety for all useful purposes) defines this parameter as the energy per unit volume lost in each deformation cycle. In other words, it is a measure of the area within the stress-strain hysteresis loop.
The Energy Loss Factor (KEL) is a function of both tan xcex4 and the elastic storage modulus (Exe2x80x2) and may be defined by the following equation:
KEL=tan xcex4*1012/[Exe2x80x2*(1+tan xcex42)]
where Exe2x80x2 is in Pascals.
The higher the value of KEL for a pad, generally the lower the elastic rebound and the lower the observed dishing.
One method to increase the KEL value for a pad is to make it softer. However, along with increasing the KEL of the pad, this method tends to also reduce the stiffness of the pad. This can reduce the pad""s planarization efficiency which is generally undesirable.
A preferred approach to increase a pad""s KEL value is to alter its physical composition in such a way that KEL is increased without reducing stiffness. This can be achieved by altering the composition of the hard segments (or phases) and the soft segments (or phases) in the pad and/or the ratio of the hard to soft segments (or phases) in the pad. This results in a preferred pad that has a suitably high hardness with an acceptably high stiffness to thereby deliver excellent planarization efficiency.
The morphology of a polymer blend can dictate its final properties and thus can affect the end-use performance of the polymer in different applications. The polymer morphology can be affected by the manufacturing process and the properties of the ingredients used to prepare the polymer. The components of the polymer used to make the polishing pad should preferably be chosen so that the resulting pad morphology is stable and easily reproducible.
In another embodiment of this invention, the glass transition temperature of the polymer used to make the polishing pad is shifted to sub-ambient temperatures without impacting the stiffness of the pad appreciably. Lowering the glass transition temperature (Tg) of the pad increases the KEL of the pad and also creates a pad whose stiffness changes very little between the normal polishing temperature range of 20xc2x0 C. and 100xc2x0 C. Thus changes in polishing temperature have minimal effect on pad physical properties, especially stiffness. This can result in more predictable and consistent performance.
A feature of one embodiment of this invention is the ability to shift the glass transition temperature to below room temperature and to design a formulation which results in the modulus above Tg being constant with increasing temperature and of sufficiently high value to achieve polishing planarity. Modulus consistency can often be improved through either crosslinking, phase separation of a xe2x80x9chardxe2x80x9d, higher softening temperature phase, or by the addition of inorganic fillers (alumina, silica, Ca CO3, etc.).
Another advantage of shifting the Tg (glass transition temperature) of the polymer to sub-ambient temperatures is that in some embodiments of the invention, the resulting pad surface can be more resistant to glazing.
Potential attributes of the pad of the present invention include:
1. High pad stiffness and pad surface hardness;
2. High energy dissipation (high KEL);
3. Stable morphology that can be reproduced easily and consistently, and which does not change significantly or adversely during polishing;
4. Pad surface that reduces glazing, thereby requiring less frequent and less aggressive conditioning, resulting in low pad wear during polishing and long pad life;
5. No porosity and surface voids thereby reducing pockets that trap used slurry and increase pad roughness. This reduces and almost eliminates a major source of defects in wafers; and/or
6. Pad chemistry can be easily altered to make it suitable for polishing a wide variety of wafers.
One or more of the above features can often translate into the following polishing benefits:
1. The high pad stiffness yields wafers that have good planarity;
2. The pad""s top layer conditions more easily and uniformly with low glazing, and this reduces scratches and LPD defects on polished IC wafers when compared to other pads, such as IC1010;
3. Lower final dishing is seen on pattern wafers even at extended overpolish times. This is attributable to the favorable combination of high KEL and high modulus;
4. Larger polish window on pattern wafers when compared to standard pads;
5. No feature specific dishing observed on pattern wafers; and/or
6. Pad stiffness changes very little between the normal polishing temperature range of 20xc2x0 C. and 100xc2x0 C. leading to a very stable and uniform polishing.
In summary:
1. Preferred pads for metal CMP generally have an optimized combination of one or more of the following: stiffness (modulus and thickness), Energy Loss Factor (KEL), modulus-temperature ratio, hardness, and surface roughness: by varying the pad composition, these can be somewhat independently controlled;
2. Pads with low elastic recovery generally produce low dishing of features during metal CMP polishing;
3. Low elastic recovery can be defined in terms of the xe2x80x9cEnergy Loss Factorxe2x80x9d (KEL);
4. Preferred ranges for these parameters are shown below:
Modulus, (Exe2x80x2) and Energy Loss Factor (KEL) are measured using the method of Dynamic Mechanical Analysis at a temperature of 40xc2x0 C. and frequency of 10 radians/sec. KEL is calculated using the equation defined earlier.
The last row defines the ratio of the modulus measured at 30xc2x0 C. and 90xc2x0 C. This represents the useful temperature range for polishing. Ideally, modulus will change as little as possible and in a linear trend with increasing temperature (i.e. ratio approaches unity). Surface roughness values are after conditioning.
From the above table, it is apparent that preferred pads of this invention will generally have a flat modulus-temperature response, a high KEL value in combination with a high modulus value, and low surface roughness after conditioning.